Programmable Networks Routers

The new design should enable much more flexible traffic management, without sacrificing speed.

Programmable Networks Routers
Image source: MIT News

Whenever network traffic in all data networks is heavy, data packets get baked up at network routers or dropped altogether. All data networks consist of control algorithms to manage network traffic while congestion period. But due to the routers, the control algorithms are hardwired into the routers’ circuitry. It means, if someone develops a better algorithm, network operators need to wait for a new hardware before taking benefit of it.

Scientists from MIT’s Computer Science in collaboration with Artificial Intelligence Laboratory (CSAIL) and five other organizations develop a programmable router. They hope to change above condition through this but can still keep up with the fiery speeds of modern data networks. Scientists design their system in a pair of papers being present at the annual conference of the Association for Computing Machinery’s Special Interest Group on Data Communication.

This research proves that you can get various flexible goals to manage traffic. It is possible during maintaining high performance of traditional routers. Previously, nobody used programmability in production. Because it was a factor of 10 or even 100 slower.

Hari Balakrishnan said, “You need to have the ability for researchers and engineers to try out thousands of ideas. With this platform, you become constrained not by hardware or technological limitations, but by your creativity. You can innovate much more rapidly.”

Each router in a data network has its own buffer. It means router’s memory bank, where it can pass packets at minimum data rates. Router also modify packet to transfer information about network conditions. For example, the packet encountered congestion, where, and for how long; it might even want to suggest new transmission rates for senders.

Computer scientists have scheduled various traffic management schemes. They also involve complex rules to discover which packets to admit to a router and which to drop, in what order to queue the packets, and what additional information to add to them all under a variety of different circumstances. Most of these schemes assure better network performance. Some of them have ever been deployed, because of hardware constraints in routers.

Scientists have set a goal to discover a set of simple computing elements. The elements could be sorted in such way to apply various traffic management schemes. They should not need to compromise the operating speeds of new generation’s best routers and without taking up too much space on-chip.

They develop a compiler for testing purpose of their design. They used it to compile seven experimental traffic management algorithms onto their proposed circuit elements. If any algorithm is not compiled, or if it requires unrealistic different circuits, they would add new, more sophisticated circuit elements to their palette.

Scientists also develop circuit elements beyond those seven algorithms. Then they execute other algorithms through their compiler. Thus they found that they compiled some combination of their simple circuit elements.

Researchers have provided the requirement for seven circuit types. Each of them is slightly more difficult than its previous. Simplest circuit type requires some simple traffic management algorithms whereas others require more complex types. But most complex circuits took only 4 percent of the area of a router chip. That means a bank of the least complex types would take up only 0.16 percent.

Scientists also told about their schedule. Although scheduler is the circuit element that orders packets in the router’s queue and extracts them for forwarding. To queuing packets according to priority, the scheduler sets transmission timing and forward them timewise. In routers, it slows down transmission rate to avoid barrier in the network or to help ensure equitable bandwidth distribution.

Thus, researchers draw circuit requirement in Verilog. (Verilog is the language electrical engineers typically use to design commercial chips.) It verifies that a router using the circuits would be fast enough to support the packet rates common in today’s high-speed networks. It also verifies that the router is able to forward a data packet every nanosecond.

Jennifer Rexford, professor of computer science at Princeton University said, “There are various problems in computer networking we’ve never been able to solve at the speed. Traffic actually flows through the network, because there wasn’t support directly in the network devices to analyze the traffic or act on the traffic as it arrives. What’s exciting about both of these works is that they really point to next-generation switch hardware that will be much, much more capable and more importantly, more programmable, so that we can really change how the network functions without having to replace the equipment inside the network.”

“At the edge of the network, applications change all the time. Who knew Pokémon Go was going to happen? It’s incredibly frustrating when applications’ needs evolve years and years more quickly than the equipment’s ability to support it. Getting the time scale of innovation inside the network to be closer to the time scale of innovation in applications is, I think, quite important,” she adds.